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HIP9011
Data Sheet November 1998 File Number 4367.1
Engine Knock Signal Processor
The HIP9011 is used to provide a method of detecting premature detonation often referred to as "Knock or Ping" in internal combustion engines. The IC is shown in the Simplified Block Diagram. The chip can select between one of two sensors, if needed for accurate monitoring or for "V" type engines. Internal control via the SPI bus is fast enough to switch sensors between each firing cycle. A programmable bandpass filter processes the signal from either of the sensor inputs. The bandpass filter can be selected to optimize the extraction the engine knock or ping signals from the engine background noise. Further single processing is obtained by full wave rectification of the filtered signal and applying it to an integrator whose output voltage level is proportional to the knock signal amplitude. The chip is under microprocessor control via a SPI interface bus.
Features
* Two Sensor Inputs * Microprocessor Programmable * Accurate and Stable Filter Elements * Digitally Programmable Gain * Digitally Programmable Time Constants * Digitally Programmable Filter Characteristics * On-Chip Crystal Oscillator * Programmable Frequency Divider * External Clock Frequencies up to 24MHz - 4, 5, 6, 8, 10, 12, 16, 20, and 24MHz * Operating Temperature Range -40oC to 125oC
Applications
* Engine Knock Detector Processor * Analog Signal Processing Where Controllable Filter Characteristics are Required
Ordering Information
PART NUMBER HIP9011AB TEMP. RANGE (oC) -40 to 125 PACKAGE 20 Ld SOIC PKG. NO. M20.3
Simplified Block Diagram
CH0FB
+
CH0NI CH1FB CH1IN CH1NI
CHANNEL SELECT SWITCHES
CH0IN
3RD ORDER ANTIALIASING FILTER
+
PROGRAMMABLE GAIN STAGE 2- 0.111 64 STEPS
PROGRAMMABLE BANDPASS FILTER 1-20kHz 64 STEPS
ACTIVE FULL WAVE RECTIFIER
PROGRAMMABLE INTEGRATOR 40 - 600s 32 STEPS
OUTPUT DRIVER INTOUT AND SAMPLE AND HOLD OSCIN CLOCK OSCOUT
PROGRAMMABLE DIVIDER TO SWITCHED CAPACITOR NETWORKS POWER SUPPLY AND BIAS CIRCUITS VMID VDD GND REGISTERS AND STATE MACHINE TEST SPI INTERFACE
SCK CS SI SO INT/HOLD
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HIP9011 Pinout
HIP9011 (SOIC) TOP VIEW
VDD GND VMID INTOUT NC NC INT/HOLD CS OSCIN 1 2 3 4 5 6 7 8 9 20 CH0NI 19 CH0IN 18 CH0FB 17 CH1FB 16 CH1IN 15 CH1NI 14 TEST 13 SCK 12 SI 11 SO
OSCOUT 10
Pin Descriptions
PIN NUMBER 1 2 3 4 5, 6 7 8 9 10 11 DESIGNATION VDD GND VMID INTOUT NC INT/HOLD CS OSCIN OSCOUT SO Five volt power input. This pin is tied to ground. This pin is connected to the internal mid-supply generator and is brought out for bypassing by a 0.022F capacitor. Buffered output of the integrator. Output signal is held by an internal Sample and Hold circuit when INT/HOLD is low. These pins are not internally connected. Do Not Use. Selects whether the chip is in the Integrate Mode (Input High) or in the Hold Mode (Input Low). This pin has an internal pull down. A low input on this pin enables the chip to communicate over the SPI bus. This pin has an internal pull-up. Input to inverter used for the oscillator circuit. A 4MHz crystal or ceramic resonator is connected between this pin and pin 10. To bias the inverter, a 1.0M to 10M resistor is usually connected between this pin and pin 10. Output of the inverter used for the oscillator. See pin 9 above. Output of the chip SPI data bus. This is a three-state output that is controlled via the SPI bus. The output is placed in the high impedance state by setting CS high when the chip is not selected. This high impedance state can also be programmed by setting the LSB of the prescaler word to 1. This will take precedence over CS. A 0 enables the active state. The Diagnostic Mode overrides these conditions. Input of the chip SPI data bus. Data length is eight bits. This pin has an internal pull-up. Input from the SPI clock. Normally low, the data is transferred to the chip internal circuitry on the falling clock edge. This pin has an internal pull up. A low on this pin places the chip in the diagnostic mode. For normal operation this pin is tied high or left open. This pin has an internal pull up. Non-inverting input of Channel one. Inverting input to channel one amplifier. A resistor is tied from this summing input to the transducer. A second resistor is tied between this pin and pin 17, CH1FB to establish the gain of the amplifier. Output of the channel one amplifier. This pin is used to apply feedback. Output of the channel zero amplifier. This pin is used to apply feedback. Inverting input to channel zero amplifier. Remainder same as channel one amplifier except feedback is applied from pin 18. Non-inverting input of Channel 0. Remainder the same as pin 16, except feedback is applied from terminal 18. DESCRIPTION
12 13 14 15 16 17 18 19 20
SI SCK TEST CH1NI CH1IN CH1FB CH0FB CH0IN CH0NI
4-2
HIP9011
Absolute Maximum Ratings DC Logic Supply, VDD . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Max
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Power Dissipation, PD For TA = -40oC to 70oC . . . . . . . . . . . . . . . . . . . . . . . 400mW Max For TA = 70oC to 125oC, Derate Linearly at . . . . . . . . . . 6mW/oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range, TSTG . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC At a Distance 1/16 1/32 inch, (1.59 0.79mm) from Case for 10s Max. (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
VDD = 5V 5%, GND = 0V, Clock Frequency 4MHz 0.1%, TA = -40oC to 125oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
DC ELECTRICAL SPECIFICATIONS Quiescent Supply Current Midpoint Voltage, Pin 3 Midpoint Voltage, Pin 3 Low Input Voltage, Pins INT/HOLD, CS, SI, SCK High Input Voltage, Pins INT/HOLD, CS, SI, SCK Hysteresis voltage, Pins INT/HOLD, CS, SI, SCK Internal Pull-Up Current Internal Pull-Down Current Low Level Output, Pin SO High Level Output, Pin SO Three-State Leakage Pin SO Low Level Output, Pin 10, OSCOUT High Level Output, Pin 10, OSCOUT SPI BUS INTERFACE AC Parametrics tCCH tCCL tPWL tPWH tSCCH tSUH tSUL tHH tHL tCSH tCIH 10 80 60 60 60 20 20 10 10 200 8 ns ns ns ns ns ns ns ns ns ns s IDD VMID VMID VIL VIH VHYST I Source CS, SI, VDD = 5.0V, Measured at GND SCK, TEST I Sink, INT/HOLD VOL VOH IL VOL VOH VDD = 5.0V, Measured at VDD ISOURCE = 1.6mA, VDD = 5.0V ISINK = 200A, VDD = 5.0V Measured at GND; VDD = 5.0V ISOURCE = 500A; VDD = 5.0V ISINK = -500A; VDD = 5.0V VDD = 5.25V, GND = 0V VDD = 5.0V, IL = 2mA Source VDD = 5.0V, IL = 0mA 2.3 2.4 70 0.85 0.01 4.8 4.4 5.0 2.45 2.5 50 -50 4.9 8.0 2.55 2.6 30 0.30 5.0 10 1.5 mA V V % of VDD % of VDD V A A V V A V V
CS Falling to SCLK Rising CS Rising to SCLK Falling SCLK Low SCLK High SCLK Falling to CS Rising Data High Setup Time Data Low Setup Time Data High Hold Time Data Low Hold Time Min Time Between 2 Programmed Words CS Rising to INT/Hold Rising
4-3
HIP9011
Electrical Specifications
PARAMETER INPUT AMPLIFIERS CH0 and CH1 High Output Voltage CH0 and CH1 Low Output Voltage Voltage Gain ANTIALIASING FILTER Response 1kHz to 20kHz, Referenced to 1kHz Attenuation at 180kHz, Referenced to 1kHz PROGRAMMABLE FILTERS Peak to Peak Voltage Output Filters Q (Note 2) PROGRAMMABLE GAIN AMPLIFIERS Percent Amplifier Gain Deviation INTEGRATOR Integrator Reset Voltage VRESET Pin 4 Voltage at Start of Integration Cycle; VDD = 5.0V Hold Mode, Pin 7 = 0V, VDD = 5.0V Pin 4 set to 20% to 80% of VDD 75 125 175 mV %G Run Mode 1 % VOUT Q Run Mode Run Mode 3.5 4.0 2.5 VP-P Q BW ATTEN Test Mode Test Mode -10 -0.5 -15 dB dB VOUTHI VOUTLO ACL ISINK = 100A, VDD = 5.0V ISOURCE = 100A; VDD = 5.0V Input R = 47.5K, Feedback R = 475k 4.7 +18 4.9 15 +20 200 +21 V mV dB VDD = 5V 5%, GND = 0V, Clock Frequency 4MHz 0.1%, TA = -40oC to 125oC, Unless Otherwise Specified (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Integrator Droop after 500s
VDROOP
-
3
50
mV
DIFFERENTIAL CONVERTER Differential to Single Ended Converter Offset Voltage Change In Converter Output SYSTEM GAIN DEVIATION Gain Deviation from "Ideal Equation" Correlation Factor + 5.0% (Note 3) VOUT VRESET Run Mode, maximum signal output from Input Amplifier <2.25VP-P , Equation Output X 0.95 + Device Reset Voltage; For Total VOUT 4.7V -8%, 100mV Equation X 0.95 - VRESET
DIFVIO DIFOUT
By Design Run Mode, 500A Sinking Load to No Load Condition
-
0.1 1
10
mV mV
8%, 100mV
V
NOTES: 2. Q = fo/BW, where: fo = Center Frequency, BW = 3dB Bandwidth 3. Ideal Equation: INTOUT (Volts) = [VIN * GIN * GPR * GBPF * 1/ * (N/tC(ms) * fQ(kHz)) * GDSE] + VRESET Where: VIN = input signal amplitude (VP-P) GIN = External Input Gain; GIN = RF/RIN GPR = Programmed Gain GBPF = Gain of Bandpass Filter (2 for Ideal Case at Center) tINT = Integration Time; tINT = N/fQ 0.318 = 1/ N = Number of Cycles of Input Signal fQ = Frequency of Input Signal RF = Feedback Resistor Value RIN = Signal Input Resistor Value tC = Programmed Time Constant GDSE = Gain of DSE Converter (2 for Ideal Case) VRESET = Integrator Reset Voltage = 0.125V, Typ
4-4
HIP9011 Timing Diagrams
INT/HOLD tCSH CS tCSCH SCK tCSCF SI tSUH SO B7 B7 tPWH B6 tHH B6 B5 B4 B3 B2 B1 B0 B5 B4 B3 B2 B1 B0 tPWL tSCCH tCIH
FIGURE 1. SPI TIMING
TABLE 1. SPI TIMING REQUIREMENTS SYMBOL tCSCH tCSCF tPWL tPWH tSCCH tSUH tSUL tHH tHL tCIH tCSH REQUIREMENT Minimum time from CS falling edge to SCK rising edge. Minimum time from CS falling edge to SCK falling edge. Minimum time for the SCK low. Minimum time for the SCK high. Minimum time from SCK falling after 8 bits to CS raising edge. Minimum time from data high to falling edge of spiclk. Minimum time from data low to falling edge of spiclk. Minimum time for data high after the falling edge of the spiclk. Minimum time for data low after the falling edge of the spiclk. Minimum time after CS raises until INT/HOLD goes high. Minimum time between programming 2 internal registers. TIME 10ns 80ns 60ns 60ns 80ns 20ns 20ns 10ns 10ns 8s 200ns
t1 INT/HOLD
t3
t2 t4
INTOUT
FIGURE 2. INTEGRATOR TIMING
TABLE 2. INTEGRATE/HOLD TIMING REQUIREMENTS SYMBOL t1 t2 t3 t4 REQUIREMENT Maximum rise time of the INT/HOLD signal. Maximum time after INT/HOLD rises for INTOUT to begin to integrate. Maximum fall time of INT/HOLD signal. Typical time after INT/HOLD goes low before chip goes into hold state. TIME 45ns 20s 45ns 20s
4-5
HIP9011
+5V
VDD VMID
HIP9011
EXAMPLE CASE USING IDEAL SYSTEM EQUATION When the Input Signal is Present for the Period tINT: INTOUT (Volts) = 1 t int V IN x G IN x G BPR x G PR x -- x ------- x G DSE + V RESET tc
SPI BUS
0.022F GND CH0NI CH1NI CH1IN Rin RF Rin RF TRANSDUCERS OSCIN 20pF 4MHz OSCOUT 20pF 1M A/D CONVERTER INTOUT TEST +5V CH1FB CH0IN CH0FB INT/HOLD SI SO SCK CS
Where: VIN = 200mVP-P, Continuous AC Signal GIN = 1.0, Ratio of RF to RIN GPR = 0.190 GBPF = 2.0 Ideal Gain Value tC = 200s tINT = 2ms GDSE = 2.0 Ideal Gain Value VRESET = 0.125V, Typical Value INTOUT (Volts) = 200x10-3*1* [2 * 0.19 * 0.318 * 2x10-3/200x10-6* 2]+0.125 = 0.4833 + 0.125 = 0.608V
MICROPROCESSOR
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE HIP9011 IN AN AUTOMOTIVE APPLICATION
Description of the HIP9011 Operation
This IC is designed to be a universal digitally controlled, analog interface between engine acoustical sensors or accelerometers and internal combustion engine fuel management systems. Two wideband input amplifiers are provided which will allow the use of two sensors. These sensors be of the piezoelectric type, that can be mounted in optimum locations on either in-line or V type engine configurations. Output from these input amplifiers are directed to a channel select mux switch and then into a 3rd order antialiasing filter. The output signal is then directed to two programmable gain stages, where one stage inverts or shifts the knock signal 180 degrees. The gain stage signals are outputted to two programmable bandpass filter stages. Outputs from the two BPF stages are then full wave rectified before being digitally integrated by the programmable integrator. The integrator output is applied to a line driver for further processing by the engine fuel management control system. The gain, bandpass filter and integrator stage settings are programmable from a microprocessor via the SPI Bus Interface Broadband piezoelectric ceramic transducers used for the engine signal pickup have device capacitances in the order of 1100pF and output voltages that range from 5mV to 8V RMS. During normal engine operation, a single input channel is selected and applied to the HIP9011. The engine background noise is typically well below in amplitude than the pre-detonation noise. Therefore, the bandpass filter stages can be optimized to further discriminate between engine background and combustion noise and predetonation noise. A basic approach to engine pre-detonation systems is to only observe engine background during the time interval that noise is expected and if detected, retard timing. This basic approach does not require the sensitivity and selectivity that is needed for a continuously adjustable solution. Enhanced fuel economy and performance is obtainable when this IC is coupled with a microprocessor controlled fuel management system.
4-6
HIP9011 Circuit Block Description
Input Amplifiers
Two amplifiers can be selected to interface to the engine sensors. These amplifiers have a typical open loop gain of 100dB, with a typical bandwidth of 2.6MHz. The common mode input voltage range extends to within 0.5V of either supply rail. The amplifier output has a similar output range. Sufficient gain, bandwidth and output swing capability is provided to ensure that the amplifier can handle attenuation gain settings of 20 to 1 or -26dB. This would be needed when high peak output signals, in the range of 8VRMS are obtained from the transducer. Gain settings of 10 times can also be needed when the transducers have output levels of 5mVRMS . In a typical application the input signal frequency may vary from 1kHz to 20kHz. External capacitors are used to decouple the IC from the sensor (C1 and C2) refer to Figure 4. A typical value of the capacitor would be 3.3nF. Series input resistors, R1 and R2, are used to connect the inverting inputs of the amplifiers, (pins 19 and 16.) Feedback resistors, R3 and R4, in conjunction with R3 and R4 are used to set the gain of the amplifiers. A mid voltage level is generated internally within the IC. This level is set to be half way between VDD and ground. Throughout the IC this level is used as a quiet, DC reference for the signal processing circuits within the IC. This point is brought out for several reasons, it can be used as a reference voltage, and it must be bypassed to insure that it remains as a quiet reference for the internal circuitry. The input amplifiers are designed with power down capability, which, when activated disables their bias circuit and their output goes into a three-state state condition. This is utilized during the diagnostic mode, in which the output terminals of the amplifiers are driven by the outside world with various test signals.
Programmable Gain Stage
The gains for two identical programmable gain stages can be adjusted, so that the knock energies can be compensated if needed. This adjustment can be made with 64 different gain settings, ranging between 2 and 0.111. The signals can swing between 20 to 80 percent of VDD . Programming is discussed in the SPI Communications Protocol section.
Programmable Bandpass Filter
Two identical programmable filters are used to detect the frequencies of interest. The Band Pass Filter (BPF) is programmed to pass the frequency component of the engine knock. The filter frequency is established by the characteristics of the particular engine and transducer. By integrating the rectified outputs from these two filters at the INTEGRATOR stage, a knock can be detected if it has occurred. The filters have a nominal differential gain of 4. Their frequency is set by a programmable word (discussed in the SPI Communications Protocol section.) Center frequencies can be programed from 1.22kHz to 19.98kHz, in 64 steps. The filter Qs are typically 2.4.
Active Full Wave Rectifier
The output of the bandpass filters are unity gain buffered prior to full wave rectification using switch capacitor techniques. Each side of the rectifier circuit provides both negative and positive values of the knock frequency bandpass frequency filter outputs. The output is able to swing from 20 to 80 percent of VDD. Care was taken to minimize the RMS variations from input to output of this stage.
Programmable Integrator Stage
The signals from the rectifier stage are separated into 2 output signal paths which are then integrated together. A differential system is used to minimize noise. One side integrates the positive energy value from the Knock Frequency Rectifier. The second side does the integration of the negative energy value. The positive and negative energy signals are opposite phase signals. Using this technique reduces system noise from affecting the actual signal. The integrator time constant is software programmable by the Integrator Time Constant discussed in the Communications Protocol section. The time constant can be programmed from 40s to 600s, with a total of 32 steps. If for example, we program a time constant to 200s, then with one volt difference between each channel, the output of the integrator will change by volt in 200s.
R4 C2 R2 VMID
Antialiasing Filter
The IC has a 3rd order Butterworth filter with a 3dB point at 70kHz. Double poly capacitors and implanted resistors are used to set poles in the filter. This filter is required to have no more than 1dB attenuation at 20kHz (highest frequency off interest) and a minimum attenuation of 10dB at 180kHz. This filter precedes the switch capacitor filter stages which run at the system frequency of 200kHz.
R3 C1 SENSOR VMID R1
19 20
+
18
SENSOR
16 15
+
17
FIGURE 4. INPUT AMPLIFIER CONNECTIONS
4-7
HIP9011
Integration is enabled by the rising edge of the input control signal INT/HOLD. Within 20s after the integrate input reaches a logic high level, the output of the integrator will fall to approximately VRESET, 0.125V. The output of the integrator is an analog voltage.
Programming Words
1. Band Pass Filter Frequency: Defines the center frequency of the Band Pass Filter in the system. The first 2 bits are used for the address and the last 6 bits are used for its value. 00FFFFFF Example: 00001010 would be the Band Pass Filter at a center frequency of 1.78kHz (bit value of 10 in Table 3). 2. Gain Control: defines the value of the gain stage attenuation of gain setting. The first 2 bits are again used for the address and the last 6 bits for its value. 10GGGGGG Example: 10010100 would be the Gain Control (10 for the first two bits) with an attenuation of 0.739 (bit value of 20 in Table 3). 3. Integrator Time Constant: Defines the Integration Time Constant for the system. The first 3 bits are used for the address and the last 5 bits for the value. 110TTTTT Example: 11000011 would be the Integrator Time Constant (110 for the first 3 bits) and an Integration Time Constant of 55s (bit value 3 in Table 3). 4. Test/Channel Select Control: Again the first three bits, 111 are the address for this function, and the last five bits define the functions that may be programmed. Example: 111B4B3B2B1B0; The options are: A) If B0 is "0", than channel 0 is selected. If B0 is "1"; than channel 1 is selected as the input. B) The remaining bits are used for selection of the various diagnostic modes. TEST pin (14) = low. Not applicable in Run Mode. 5. Prescaler/SO terminal status: Defines the division ratio of the internal frequency prescaler and the status of the SO terminal, pin 11. P1 to P4 bits define the frequency that may be used with an external clock. The status of the three state SO pin is set by the last, Z bit. 01P5P4P3P2P1Z; Example: 0100000, Note, in this case bit P5 is not used. (01 for the first 2 bits sets the Prescaler/SO function) P1 to P4 set Prescaler for a clock frequency of 4MHz and the last bit sets the S0 terminal to an active state.
Differential to Single-Ended Converter
This circuit takes the differential output of the integrators (through the test-multiplexer circuit) and provides a signal that is the sum of the two signals. This technique is used to improve the noise immunity of the system.
Output Buffer
This output amplifier is the same amplifier circuits as the input amplifier used to interface with the sensors. For diagnostic purposes when the output of the antialias filter is being evaluated, this amplifier is in the power down mode.
Test Multiplexer
This circuit receives the positive and negative outputs from the integrator, together with the outputs from different parts of the IC. The Test Mux output is controlled by the fifth programming word of the communications protocol. This multiplexes the switch capacitor filter output, the gain control output and the antialias filter output.
SPI Communications Protocol
Communicating to the Knock Sensor via the SPI Bus (MOSI). A chip select pin (CS) is used to enable the chip, which, in conjunction with the SPI clock (SCK), which moves an eight bit programming word. Five different programming words are used to set the following internal programmable registers: GAIN, BANDPASS FREQUENCY FILTER, INTEGRATOR TIME CONSTANT, CHANNEL SELECT, SO output mode, and TEST MODES. When chip select (CS) goes low, on the next falling edge of the SPI clock (SCK), data is latched into the SPI register. The data is shifted with the most significant bit first and least significant bit last. Each word is divided into two parts: first the address and then the value. Depending on the function being controlled, the address is 2 or 3 bits, and the value is either 5 or 6 bits long. All five programming words can be entered into the IC during the HOLD mode of operation. The integration or hold mode of operation is controlled by the INT/HOLD input signal.
4-8
HIP9011
TABLE 3. FREQUENCY, GAIN, AND INTEGRATOR TIME CONSTANT BIT VALUE PER FUNCTION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FREQUENCY (kHz) 1.22 1.26 1.31 1.35 1.40 1.45 1.51 1.57 1.63 1.71 1.78 1.87 1.96 2.07 2.18 2.31 2.46 2.54 2.62 2.71 2.81 2.92 3.03 3.15 3.28 3.43 3.59 3.76 3.95 4.16 4.39 4.66 GAIN 2.000 1.882 1.778 1.684 1.600 1.523 1.455 1.391 1.333 1.280 1.231 1.185 1.143 1.063 1.000 0.944 0.895 0.850 0.810 0.773 0.739 0.708 0.680 0.654 0.630 0.607 0.586 0.567 0.548 0.500 0.471 0.444 TIME CONSTANT (s) 40 45 50 55 60 65 70 75 80 90 100 110 120 130 140 150 160 180 200 220 240 260 280 300 320 360 400 440 480 520 560 600 BIT VALUE PER FUNCTION 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 FREQUENCY (kHz) 4.95 5.12 5.29 5.48 5.68 5.90 6.12 6.37 6.64 6.94 7.27 7.63 8.02 8.46 8.95 9.50 10.12 10.46 10.83 11.22 11.65 12.10 12.60 13.14 13.72 14.36 15.07 15.84 16.71 17.67 18.76 19.98 GAIN 0.421 0.400 0.381 0.364 0.348 0.333 0.320 0.308 0.296 0.286 0.276 0.267 0.258 0.250 0.236 0.222 0.211 0.200 0.190 0.182 0.174 0.167 0.160 0.154 0.148 0.143 0.138 0.133 0.129 0.125 0.118 0.111
TABLE 4. PRESCALER CLOCK FREQUENCY (MHz) 4 5 6 8 10 12 16 20 24 P5 X X X X X X X X X P4 0 0 0 0 0 0 0 0 1 P3 0 0 0 0 1 1 1 1 0 P2 0 0 1 1 0 0 1 1 0 P1 0 1 0 1 0 1 0 1 0
TABLE 5. SO TERMINAL STATUS SO TERMINAL STATUS High Impedance SO Terminal Active Z 1 0
NOTE: X = Don't care, P5 not used.
4-9
HIP9011
ADDRESS DECODER
SI
PRESCALER/SO TERMINAL STATUS
GAIN CONTROL
DIGITAL MULTIPLEXER
SCK
SPI INTERFACE
BANDPASS FILTER
CS
INTEGRATOR TIME CONSTANT
SO
TEST/CHANNEL SELECT CONTROL SI TEST COMP OUT
FIGURE 5. PROGRAMMABLE REGISTERS AND STATE MACHINE
The Digital SPI Block diagram in Figure 5 shows the programming flow of the chip. An eight bit word is received at the SI port. Data is shifted in by the SCK clock when the chip is enable by the CS pin. The word is decoded by the address decoding circuit, and the information is directed to one of 5 registers. These registers control the following chip functions: 1. Band Pass Filter frequency. 2. Gain control or attenuation. 3. Integration time constant of the rectified BPF output. 4. Prescaler. 5. Test/Channel Select. a) Test conditions of the part. b) Channel select to one of two input amplifiers. A crystal oscillator circuit is provided. The chip requires at minimum a 4MHz crystal to be connected across OSCIN and OSCOUT pins. An external 4MHz signal may also be provided to the OSCIN Terminal Pin 9.
In the diagnostic mode, we can use the digital multiplexer to output one of the following results through the SO pin (11): 1. Value of one of the five registers in the chip 2. Buffered value of the SI pin (12). 3. Value of an internal comparator used to rectify the analog signal A digital SPI filter is located in the SPI Block which provides a pseudo noise immunity characteristic. The digital SPI filter operation requires that the SCK be low prior to the fall of CS, followed by 8 SCK pulses (low-highlow transitions). With the SCK ending the pulse sequence in a logic low condition, the transition of CS from a low to high transition will cause the data-word in the SPI Buffer to be loaded into the proper addressed programmable register. During the Integration mode, INT/HOLD pin is high, any single SPI byte that is entered will be acted upon if the conditions of the digital SPI filter are met. The digital SPI filter allows for only 8 bits per word to be accepted.
4-10
HIP9011 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A MIN 0.0926 0.0040 0.013 0.0091 0.4961 0.2914 MAX 0.1043 0.0118 0.0200 0.0125 0.5118 0.2992 MILLIMETERS MIN 2.35 0.10 0.33 0.23 12.60 7.40 MAX 2.65 0.30 0.51 0.32 13.00 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
L
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.394 0.010 0.016 20 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 20 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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